1. Field of the Invention
This invention relates generally to methods for forming a uniform layer of material on a substrate such, as a semiconductor wafer. More particularly, the invention relates to methods for forming a uniform layer of dielectric material on a semiconductor structure, especially a non-planar semiconductor structure.
2. State of the Art
The fabrication of semiconductor devices involves forming electronic components on semiconductor substrates, such as silicon wafers. These electronic components may include transistors, resistors, and the like, with intermediate and overlying metallization patterns at varying levels which interconnect the electrical components to form circuits. The formation of these circuits results in uneven or non-planar topography on an active surface of the semiconductor device.
Generally during the fabrication of these semiconductor devices, numerous layers of materials are deposited on the active surface of the semiconductor device. Some of the most important layers comprise insulative layers made from dielectric materials. Dielectric materials, such as polymeric materials, such as polyimides, and glasses, such as spin-on-glass (SOG) or other silicon-based glass including boron, phosphorous, and boron/phosphorous silicate glasses, and silicon nitride, are used to form electrically insulative interlevel layers as well as to form final protective (e.g., passivation) coatings over the semiconductor device. These dielectric materials are particularly useful as interlevel layers because they fin in gaps in the non-planar semiconductor device topography, and also generally form self-leveling, highly planar surfaces. The formation of a planar surface may eliminate the need for mechanical or chemical/mechanical planarizing the interlevel layer before depositing additional metallization or electronic components thereon.
Dielectric materials, whether polymeric materials or spin-on-glasses, are usually applied in a fluid state to the semiconductor wafer while the semiconductor wafer is rotated at a constant speed of about 500 to 5000 rpm. The application of the dielectric material is generally complete in a few seconds. Of course, other processes known in the art can be used for applying the dielectric material layer to semiconductor devices, such as chemical vapor deposition (CVD), plasma CVD, extrusion, and sputtering. One problem with these processes is that very specialized equipment and procedures are required. Furthermore, these processes and equipment used in these processes may be incompatible with the manufacturing conventions in use.
Current trends in size reduction of semiconductor devices leading to tighter or lower pitches and higher aspect ratios are making the current methods of applying layers of materials, particularly dielectric materials, unworkable. First, a greater number of layers of electronic components, sometimes five or more, are being applied to a substrate surface which increases the height of the circuit topography on the substrate surface. Second, metallization patterns are becoming more dense due to the lower pitch, with less lateral space between conductive traces. Third, in order to accommodate the greater density of conductive traces in the metallization pattern, the width of the conductive traces must be reduced. However, to compensate for the reduced conductive trace width, the thickness or height of the conductive traces must be proportionately increased to maintain the requisite current through the conductive traces.
These trends combine to produce very high aspect ratios (height of a circuit element or combination of elements in comparison to the width or valley between adjacent elements or combination of elements) in the topography of the semiconductor device. However, the high aspect ratio topography may cause (a) non-conformal penetration of the layering material which results in portions of the valleys being devoid of dielectric material; (b) the formation of small gas-filled bubbles or "voids" in the layering material resulting from gas in the valleys becoming trapped during the application of the layering material thereby entraining the bubbles in the dielectric layer; and (c) the formation of non-planar (non-uniform) dielectric layer surface topography.
FIG. 5 illustrates a simplified cross-sectional view of a high aspect ratio semiconductor device 200 which has been prepared by a prior art method. One or more layers of metallization or other materials 202, together with a silicon oxide layer 204, form projections 206 on a surface 208 of a substrate 210. Thus, projections 206 create a non-planar semiconductor surface 212. A layer of dielectric material 214 is shown as applied to the non-planar semiconductor surface 212 by a conventional spinning process. For reasons discussed above, the dielectric material 214 may not flow into the valleys 216 between the projections 206. This results in either the formation of small gas-filled bubbles or "voids" 218 in the dielectric material 214, or the formation of areas of non-conformal penetration or gaps 220 in the dielectric material 214 over the valleys 216. Furthermore, the result of this prior art technique is generally a non-planar top surface 222.
If the dielectric material, whether as an intermediate layer or final coating, fails to fully cover portions of the semiconductor device, the device may fail to meet the required test specifications, and thus must be discarded. Such loss is expensive and highly undesirable. Additionally, the formation of gas-filled "voids" is troublesome since it results in non-uniform insulative properties in the dielectric material which may not manifest themselves during burn-in or testing, but only during long term operation. Furthermore, when portions of the semiconductor device are exposed to any oxygen present in a trapped gas bubble, chemical reactions and degradation of a component may result. This oxidation may cause premature failure of the semiconductor device. Moreover, non-planarity of an intermediate dielectric surface necessitates a further step of planarization before further electronic components can be formed on the intermediate dielectric surface. The addition of the planarization step increases the cost of semiconductor device fabrication, which, in turn, increases the cost of the semiconductor device.
Therefore, it would be advantageous to develop a technique for forming uniform material layers, particularly planar dielectric material intermediate and final coating layers, on a semiconductor device which are substantially devoid of gaps and/or voids, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and apparatus and without requiring complex processing steps.